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Module Ast.Widen_mul2

Witness types for widening multiply upper half (SMULL2, UMULL2). Sources are 128-bit, dest is wide. 16B,16B->8H, 8H,8H->4S, 4S,4S->2D

type ('src_arr, 'src_w, 'dst_arr, 'dst_w) t =
  1. | V8H_V16B : ([ `V16B ], [ `B ], [ `V8H ], [ `H ]) t
  2. | V4S_V8H : ([ `V8H ], [ `H ], [ `V4S ], [ `S ]) t
  3. | V2D_V4S : ([ `V4S ], [ `S ], [ `V2D ], [ `D ]) t