Module `Arm64_binary_emitter.Add_sub_helpers`

val decode_shift_kind_int : 'a Arm64_ast.Ast.Operand.Shift.Kind.t -> int

val decode_shift_amount_six : 'a Arm64_ast.Ast.Immediate.t -> int

Extract shift amount from an Imm.t. Used for shifted register operations where the instruction types guarantee a Six immediate, but OCaml can't prove this statically due to < constraints.

val is_sp_reg : 'a Arm64_ast.Ast.Reg.t -> bool

val encode_add_sub_shifted_register : 
  sf:int ->
  op:int ->
  s:int ->
  shift:int ->
  rm:int ->
  imm6:int ->
  rn:int ->
  rd:int ->
  int32

val encode_add_sub_extended_register : 
  sf:int ->
  op:int ->
  s:int ->
  rm:int ->
  option:int ->
  imm3:int ->
  rn:int ->
  rd:int ->
  int32

val encode_add_sub_immediate : 
  sf:int ->
  op:int ->
  s:int ->
  sh:int ->
  imm12:int ->
  rn:[ `GP of 'a ] Arm64_ast.Ast.Reg.t ->
  rd:[ `GP of 'b ] Arm64_ast.Ast.Reg.t ->
  int32

val encode_add_sub_imm_auto_shift : 
  op:int ->
  s:int ->
  imm12:int ->
  shift_opt:'a option ->
  rn:[ `GP of 'b ] Arm64_ast.Ast.Reg.t ->
  rd:[ `GP of 'c ] Arm64_ast.Ast.Reg.t ->
  int32

val encode_add_sub_shifted_reg : 
  op:int ->
  s:int ->
  shift:int ->
  imm6:int ->
  rd:[ `GP of 'a ] Arm64_ast.Ast.Reg.t ->
  rn:[ `GP of 'b ] Arm64_ast.Ast.Reg.t ->
  rm:[ `GP of 'c ] Arm64_ast.Ast.Reg.t ->
  int32

Module Arm64_binary_emitter.Add_sub_helpers

Module `Arm64_binary_emitter.Add_sub_helpers`