Module `Regs`

type reg_class =

| GPR
(*
64-bit integer registers. The same name is used regardless of the width of the value stored in the register.
*)
| SIMD
(*
128/256/512-bit SIMD registers. Different names are used when storing different sized values.
*)

type _ phys_reg_classed =

type phys_reg =

val phys_gpr_regs_classed : [ `GPR ] phys_reg_classed array

val phys_gpr_regs : phys_reg array

val phys_simd_regs_classed : [ `SIMD ] phys_reg_classed array

val phys_simd_regs : phys_reg array

include Regs_utils.T
  with type Reg_class.t = reg_class
  with type Phys_reg.t = phys_reg

module Reg_class : sig ... end

module Phys_reg : sig ... end

val index_in_class : Phys_reg.t -> int

val registers : Reg_class.t -> Phys_reg.t array

val available_registers : Reg_class.t -> Phys_reg.t array

val num_available_registers : Reg_class.t -> int

val register_name : Cmm.machtype_component -> Phys_reg.t -> string

val dwarf_reg_number : Cmm.machtype_component -> Phys_reg.t -> int

module Reg_class_tbl : Regs_utils.Reg_class_tbl with type reg_class = reg_class

module Save_simd_regs : sig ... end

val gc_regs_offset : 
  simd:Save_simd_regs.t ->
  Cmm.machtype_component ->
  Phys_reg.t ->
  int

Module Regs