jon.recoil.org

Module Simd

include module type of struct include Amd64_simd_defs end
type ext = Amd64_simd_defs.ext =
  1. | SSE
  2. | SSE2
  3. | SSE3
  4. | SSSE3
  5. | SSE4_1
  6. | SSE4_2
  7. | POPCNT
  8. | LZCNT
  9. | PCLMULQDQ
  10. | BMI
  11. | BMI2
  12. | AVX
  13. | AVX2
  14. | F16C
  15. | FMA
type reg = Amd64_simd_defs.reg =
  1. | RAX
  2. | RDI
  3. | RCX
  4. | RDX
  5. | XMM0
type temp = Amd64_simd_defs.temp =
  1. | R8
  2. | R16
  3. | R32
  4. | R64
  5. | M8
  6. | M16
  7. | M32
  8. | M64
  9. | M128
  10. | M256
  11. | MM
  12. | XMM
  13. | YMM
  14. | VM32X
  15. | VM32Y
  16. | VM64X
  17. | VM64Y
type loc = Amd64_simd_defs.loc =
  1. | Pin of reg
  2. | Temp of temp array
type loc_enc = Amd64_simd_defs.loc_enc =
  1. | RM_r
  2. | RM_rm
  3. | Vex_v
  4. | Implicit
  5. | Immediate
type arg = Amd64_simd_defs.arg = {
  1. loc : loc;
  2. enc : loc_enc;
}
type res = Amd64_simd_defs.res =
  1. | Res_none
  2. | Arg of int array
  3. | Res of arg array
type legacy_prefix = Amd64_simd_defs.legacy_prefix =
  1. | Prx_none
  2. | Prx_66
  3. | Prx_F2
  4. | Prx_F3
type legacy_rex = Amd64_simd_defs.legacy_rex =
  1. | Rex_none
  2. | Rex
  3. | Rex_w
type legacy_escape = Amd64_simd_defs.legacy_escape =
  1. | Esc_none
  2. | Esc_0F
  3. | Esc_0F38
  4. | Esc_0F3A
type vex_map = Amd64_simd_defs.vex_map =
  1. | Vexm_0F
  2. | Vexm_0F38
  3. | Vexm_0F3A
type prefix = Amd64_simd_defs.prefix =
  1. | Legacy of {
    1. prefix : legacy_prefix;
    2. rex : legacy_rex;
    3. escape : legacy_escape;
    4. operand_size_override : bool;
    }
  2. | Vex of {
    1. vex_m : vex_map;
    2. vex_w : bool;
    3. vex_l : bool;
    4. vex_p : legacy_prefix;
    }
type rm_reg = Amd64_simd_defs.rm_reg =
  1. | Reg
  2. | Spec of int
type enc = Amd64_simd_defs.enc = {
  1. prefix : prefix;
  2. rm_reg : rm_reg;
  3. opcode : int;
}
type imm = Amd64_simd_defs.imm =
  1. | Imm_none
  2. | Imm_reg
  3. | Imm_spec
val equal_reg : reg -> reg -> bool
val equal_temp : temp -> temp -> bool
val equal_loc : loc -> loc -> bool
val temp_is_reg : temp -> bool
val temp_is_vm : temp -> bool
val loc_allows_reg : loc -> bool
val loc_allows_mem : loc -> bool
val loc_is_pinned : loc -> reg option
val loc_reg_count : loc -> int
val unarized_reg_index : arg array -> int -> int
val arg_is_implicit : arg -> bool
val ext_to_string : ext -> string
val exts_to_string : ext array -> string
module Layout = Amd64_simd_defs.Layout
val loc_register_width : loc -> Layout.reg option
val loc_memory_width : loc -> Layout.mem
module Amd64_simd_instrs : sig ... end
module Pcompare_string : sig ... end
module Seq : sig ... end
module Pseudo_instr : sig ... end
type operation = {
  1. instr : Pseudo_instr.t;
  2. imm : int option;
}
val instruction : Amd64_simd_instrs.instr -> int option -> operation
val sequence : Seq.t -> int option -> operation
type operation_class =
  1. | Pure
  2. | Load of {
    1. is_mutable : bool;
    }
  3. | Store
val class_of_operation : operation -> operation_class
val is_memory_operation : operation -> bool
val is_pure_operation : operation -> bool
val equal_operation : operation -> operation -> bool
val print_operation : ?addr:((Format.formatter -> 'a array -> unit) * int) -> (Format.formatter -> 'a -> unit) -> operation -> Format.formatter -> 'a array -> unit
module Mem : sig ... end