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Module Ast.DSL

val reg_op : 'a Reg.t -> [ `Reg of 'a ] Operand.t
val imm : int -> [ `Imm of [ `Twelve ] ] Operand.t
val imm_six : int -> [ `Imm of [ `Six ] ] Operand.t
val imm_sixteen : int -> [ `Imm of [ `Sixteen_unsigned ] ] Operand.t
val imm_sixteen_of_nativeint : nativeint -> [ `Imm of [ `Sixteen_unsigned ] ] Operand.t

Like imm_sixteen but takes a nativeint and validates it's in range 0, 65535. Raises Misc.fatal_error if out of range.

val imm_float : float -> [ `Imm of [ `Sixty_four ] ] Operand.t
val imm_nativeint : nativeint -> [ `Imm of [ `Sixty_four ] ] Operand.t
val bitmask : nativeint -> [ `Bitmask ] Operand.t
val symbol : 'w Symbol.t -> [ `Imm of [ `Sym of 'w ] ] Operand.t
val shift : kind:'op Operand.Shift.Kind.t -> amount:int -> [ `Shift of 'op * [ `Six ] ] Operand.t
val optional_shift : kind:'op Operand.Shift.Kind.t -> amount:int -> [ `Optional of [ `Shift of 'op * [ `Six ] ] option ] Operand.t
val lsl_by_multiple_of_16_bits : int -> [ `Lsl_by_multiple_of_16_bits of [ `X ] ] Operand.t

Create an LSL shift for MOVK/MOVN/MOVZ. The amount must be one of 0, 16, 32, or 48. Returns X-typed shift since 32 and 48 are X-only. For W-form, use lsl_by_multiple_of_16_bits_w which only accepts 0 and 16.

val lsl_by_multiple_of_16_bits_w : int -> [ `Lsl_by_multiple_of_16_bits of [ `W ] ] Operand.t

Create an LSL shift for W-form MOVK/MOVN/MOVZ. Only accepts 0 or 16.

val optional_lsl_by_multiple_of_16_bits : int -> [ `Optional of [ `Lsl_by_multiple_of_16_bits of [ `X ] ] option ] Operand.t
val optional_lsl_by_multiple_of_16_bits_w : int -> [ `Optional of [ `Lsl_by_multiple_of_16_bits of [ `W ] ] option ] Operand.t
val shift_by_element_width_b : int -> [ `Shift_by_element_width of [ `B ] ] Operand.t

Create a shift amount for SHL/SSHR/USHR on B (8-bit) elements. Valid range: 0-7.

val shift_by_element_width_h : int -> [ `Shift_by_element_width of [ `H ] ] Operand.t

Create a shift amount for SHL/SSHR/USHR on H (16-bit) elements. Valid range: 0-15.

val shift_by_element_width_s : int -> [ `Shift_by_element_width of [ `S ] ] Operand.t

Create a shift amount for SHL/SSHR/USHR on S (32-bit) elements. Valid range: 0-31.

val shift_by_element_width_d : int -> [ `Shift_by_element_width of [ `D ] ] Operand.t

Create a shift amount for SHL/SSHR/USHR on D (64-bit) elements. Valid range: 0-63.

val optional_none : [ `Optional of 'a option ] Operand.t
val unit_operand : unit Operand.t
val mem : base:[ `GP of [< `X | `SP ] ] Reg.t -> [ `Mem of [> `Base_reg ] ] Operand.t
module Validated_mem_offset : sig ... end

A validated memory offset that is guaranteed to be encodable in ARM64 load/store immediate addressing modes. The validation ensures:

type 'a mem_offset_result = private
  1. | Ok of 'a
  2. | Offset_out_of_range

Result type for mem_offset. Either Ok operand if the offset can be encoded directly, or Offset_out_of_range if a multi-instruction sequence is needed.

An offset can be encoded when:

  • The offset is in the 9-bit signed unscaled range: -256 to 255, OR
  • The offset is non-negative, aligned to the access size, and in the 12-bit unsigned scaled range (max offset depends on scale)
val mem_offset : base:[ `GP of [< `X | `SP ] ] Reg.t -> scale:int -> offset:int -> [ `Mem of [> `Offset_twelve_unsigned_scaled | `Offset_nine_signed_unscaled ] ] Operand.t mem_offset_result

mem_offset ~base ~scale ~offset creates a memory operand for accessing base + offset. The scale parameter is the access size in bytes (1, 2, 4, 8, or 16) and determines both the alignment requirement for the scaled encoding and the maximum encodable offset.

val mem_symbol : base:[ `GP of [< `X | `SP ] ] Reg.t -> symbol:[ `Twelve ] Symbol.t -> [ `Mem of [> `Offset_sym ] ] Operand.t
val mem_pre : base:[ `GP of [< `X | `SP ] ] Reg.t -> offset:int -> [ `Mem of [> `Pre ] ] Operand.t
val mem_post : base:[ `GP of [< `X | `SP ] ] Reg.t -> offset:int -> [ `Mem of [> `Post ] ] Operand.t
val mem_offset_pair : base:[ `GP of [< `X | `SP ] ] Reg.t -> offset:int -> [ `Mem of [> `Offset_pair ] ] Operand.t
val mem_pre_pair : base:[ `GP of [< `X | `SP ] ] Reg.t -> offset:int -> [ `Mem of [> `Pre_pair ] ] Operand.t
val mem_post_pair : base:[ `GP of [< `X | `SP ] ] Reg.t -> offset:int -> [ `Mem of [> `Post_pair ] ] Operand.t
val cond : Cond.t -> [ `Cond ] Operand.t
val float_cond : Float_cond.t -> [ `Float_cond ] Operand.t
val reg_v2d : int -> [ `Reg of [ `Neon of [ `Vector of [ `V2D ] * [ `D ] ] ] ] Operand.t

The functions below are shorthands for composing reg_op and the respective function from Reg

val reg_v2s : int -> [ `Reg of [ `Neon of [ `Vector of [ `V2S ] * [ `S ] ] ] ] Operand.t
val reg_v4s : int -> [ `Reg of [ `Neon of [ `Vector of [ `V4S ] * [ `S ] ] ] ] Operand.t
val reg_v8b : int -> [ `Reg of [ `Neon of [ `Vector of [ `V8B ] * [ `B ] ] ] ] Operand.t
val reg_v16b : int -> [ `Reg of [ `Neon of [ `Vector of [ `V16B ] * [ `B ] ] ] ] Operand.t
val reg_v8h : int -> [ `Reg of [ `Neon of [ `Vector of [ `V8H ] * [ `H ] ] ] ] Operand.t
val reg_v4h : int -> [ `Reg of [ `Neon of [ `Vector of [ `V4H ] * [ `H ] ] ] ] Operand.t
val reg_b : int -> [ `Reg of [ `Neon of [ `Scalar of [ `B ] ] ] ] Operand.t
val reg_s : int -> [ `Reg of [ `Neon of [ `Scalar of [ `S ] ] ] ] Operand.t
val reg_d : int -> [ `Reg of [ `Neon of [ `Scalar of [ `D ] ] ] ] Operand.t
val reg_q : int -> [ `Reg of [ `Neon of [ `Scalar of [ `Q ] ] ] ] Operand.t
val reg_x : int -> [ `Reg of [ `GP of [ `X ] ] ] Operand.t
val reg_w : int -> [ `Reg of [ `GP of [ `W ] ] ] Operand.t
val sp : [ `Reg of [ `GP of [ `SP ] ] ] Operand.t
val lr : [ `Reg of [ `GP of [ `LR ] ] ] Operand.t
val fp : [ `Reg of [ `GP of [ `FP ] ] ] Operand.t
val xzr : [ `Reg of [ `GP of [ `XZR ] ] ] Operand.t
val wzr : [ `Reg of [ `GP of [ `WZR ] ] ] Operand.t
val reglane_v4s : int -> lane:Neon_reg_name.Lane_index.t -> [ `Reg of [ `Neon of [ `Lane of [ `Vector of [ `V4S ] * [ `S ] ] ] ] ] Operand.t
val reglane_v2d : int -> lane:Neon_reg_name.Lane_index.t -> [ `Reg of [ `Neon of [ `Lane of [ `Vector of [ `V2D ] * [ `D ] ] ] ] ] Operand.t
val reglane_b : int -> lane:Neon_reg_name.Lane_index.t -> [ `Reg of [ `Neon of [ `Lane of [ `Scalar of [ `B ] ] ] ] ] Operand.t
val reglane_h : int -> lane:Neon_reg_name.Lane_index.t -> [ `Reg of [ `Neon of [ `Lane of [ `Scalar of [ `H ] ] ] ] ] Operand.t
val reglane_s : int -> lane:Neon_reg_name.Lane_index.t -> [ `Reg of [ `Neon of [ `Lane of [ `Scalar of [ `S ] ] ] ] ] Operand.t
val reglane_d : int -> lane:Neon_reg_name.Lane_index.t -> [ `Reg of [ `Neon of [ `Lane of [ `Scalar of [ `D ] ] ] ] ] Operand.t
val print_ins : ('num, 'operands) Instruction_name.t -> ('num, 'operands) many -> string
module Acc : sig ... end