jon.recoil.org

Module Arm64_ast.Ast

Typed DSL for AArch64 assembly instructions.

The same physical register has different names in the assembly encoding of instructions. The name determines the type of data the instruction operates on.

type any_vector = [
  1. | `V8B
  2. | `V16B
  3. | `V4H
  4. | `V8H
  5. | `V2S
  6. | `V4S
  7. | `V1D
  8. | `V2D
]
type any_width = [
  1. | `B
  2. | `H
  3. | `S
  4. | `D
]
module Element_to_GP : sig ... end

Constraint tying vector element width to GP register width for INS and UMOV.

module Smov_element_to_GP : sig ... end

Constraint tying vector element width to GP register width for SMOV.

module Neon_reg_name : sig ... end
module GP_reg_name : sig ... end
module Reg_name : sig ... end
module Reg : sig ... end
module Symbol : sig ... end

Symbol references and relocations.

module Float_cond : sig ... end
module Cond : sig ... end
module Branch_cond : sig ... end

Condition codes for B.cond instruction. Unifies integer and floating-point conditions - architecturally it's the same instruction, but we preserve the distinction for semantic clarity.

module Simd_int_cmp : sig ... end

Condition codes for AdvSIMD integer compare instructions. These map to CMEQ, CMGE, CMGT, CMLE, CMLT, CMHI, CMHS instructions. Unlike Cond.t, this excludes conditions that don't have corresponding SIMD compare instructions (NE, CS, CC, MI, PL, VS, VC, LS).

module Immediate : sig ... end

Immediates used in instruction operands.

module Addressing_offset : sig ... end

Offsets used in addressing modes.

module Addressing_mode : sig ... end
module Operand : sig ... end
module Rounding_mode : sig ... end
module Memory_barrier : sig ... end
type singleton = [
  1. | `Singleton
]
type pair = [
  1. | `Pair
]
type triple = [
  1. | `Triple
]
type quad = [
  1. | `Quad
]
type (_, _) many =
  1. | Singleton : 'a Operand.t -> (singleton, 'a) many
  2. | Pair : 'a Operand.t * 'b Operand.t -> (pair, 'a * 'b) many
  3. | Triple : 'a Operand.t * 'b Operand.t * 'c Operand.t -> (triple, 'a * 'b * 'c) many
  4. | Quad : 'a Operand.t * 'b Operand.t * 'c Operand.t * 'd Operand.t -> (quad, 'a * 'b * 'c * 'd) many
module Widen : sig ... end

Witness types for widening vector operations. Widening: element count stays the same, element size doubles. 8B->8H, 4H->4S, 2S->2D

module Narrow : sig ... end

Witness types for narrowing vector operations. Narrowing: element count stays the same, element size halves. 8H->8B, 4S->4H, 2D->2S

module Narrow2 : sig ... end

Witness types for narrowing to upper half (XTN2, etc). 16B->8H, 8H->4S, 4S->2D

module Widen_mul : sig ... end

Witness types for widening multiply (SMULL, UMULL). Sources are narrow, dest is wide. 8B,8B->8H, 4H,4H->4S, 2S,2S->2D

module Widen_mul2 : sig ... end

Witness types for widening multiply upper half (SMULL2, UMULL2). Sources are 128-bit, dest is wide. 16B,16B->8H, 8H,8H->4S, 4S,4S->2D

module LDP_STP_width : sig ... end

Witness types for LDP/STP register width. Both registers in a pair must be the same width class.

module Instruction_name : sig ... end

The intention is that none of these are aliases. Expansions of instructions that are aliases are done by the "ins_*" functions below.

module Instruction : sig ... end
module DSL : sig ... end